(1) Field of the Invention
The present invention relates to a phase synchronization pull-in system which is used in a bit error detecting apparatus.
Bit error detecting apparatuses are provided in digital communication systems for monitoring a malfunction in an apparatus which is used in the digital communication system. The apparatus which is monitored is, for example, a multiplexer, a demultiplexer, a coder, a decoder, or the like. The bit error detection is carried out by inversely processing the output of the apparatus being monitored so that the corresponding input is obtained when the apparatus functions normally, and comparing the inversely processed result with a corresponding actual input of the apparatus. To carry out the above inverse processing, a standard circuit which is assumed to operate normally is provided.
Further, to obtain the above correspondence between the above actual input signals of the apparatus and the corresponding output signals of the standard circuit, phases of the actual input signals of the apparatus and the corresponding output signals of the standard circuit need to be synchronized. An operation for obtaining information for the phase synchronization is carried out before a monitoring cycle, and is called phase synchronization pull in.
(2) Description of the Related Art
FIG. 1 is a block diagram of a data processing apparatus for monitoring its own main function using bit error detection.
In FIG. 1, reference numeral 50 denotes a data processing apparatus, for example, a digital transmission terminal apparatus, 51 denotes a circuit which is subject to monitoring of its own function, 52 denotes a standard circuit which carries out an inverse processing to the processing in the circuit 50, 53 denotes a bit matching circuit, 54 denotes a phase synchronization circuit, 55 denotes a bit error detecting circuit, 56 denotes a controller, and 57 and 58 denote transmission lines, respectively connected to input and output sides of the circuit 51. When the circuit 51 is a multiplexer, the standard circuit is a demultiplexer, and when the digital transmission terminal apparatus 50 has a stand-by construction (not shown) for its own currently operating construction, a demultiplexer in the stand-by construction can be used.
A signal A which contains a plurality of channels and is transmitted through the transmission line 57, is input into the circuit (multiplexer) 51, and is multiplexed, and the output B of the multiplexer 51 is transmitted out onto the transmission line 58. To monitor the operation of the multiplexer 51, the output B of the multiplexer 51 is also input into the standard circuit (demultiplexer) 52, and is demultiplexed. A signal C of a selected channel of the demultiplexed signal B, is input into the bit matching circuit 53 together with a signal of the same channel in the input signal A. Although not shown, selectors are used for the above selections of the channel, respectively. If a phase synchronization pull-in operation is impossible, the inputs of the bit matching circuit 53 may be changed to another channel.
Generally, the circuit 51 and the standard circuit 52 are formed by various digital circuit components such as flip-flop circuits, and a delay is generated through the circuit 51 and the standard circuit 52. As mentioned before, to carry out the bit error detection, correspondence between the inputs of the bit matching circuit 53 must be obtained, i.e., phases of the actual input signals of the phases of the circuit 51 and the corresponding output signals of the standard circuit 52 need to be synchronized.
To synchronize the above signals, a phase synchronization circuit 54 is provided in the first stage of the bit matching circuit 53. After the phases of the input signals are synchronized, the input signals are compared bit by bit, and a difference between the corresponding bits in the input signals, is detected as a bit error in the bit error detecting circuit 55. The aforementioned phase synchronization pull-in operation, and the monitoring of the circuit 51 following the phase synchronization pull-in, are carried out using the phase synchronization circuit 54 and the bit error detecting circuit 55 under the control of the controller 56, as explained later. The controller 56 controls the switching from the currently operating system to the stand-by system, based on the result of the monitoring.
FIG. 2 is a block diagram of the phase synchronization circuit 54 and the bit error detecting circuit 55 shown in FIG. 1.
In FIG. 2, reference numerals 61 and 62 each denote a flip-flop circuit, 63 denotes an elastic memory, 64 denotes a fixed delay circuit, 65 denotes a variable delay circuit, 66 denotes an exclusive OR circuit, 67 denotes a flip-flop circuit, and 68 denotes an AND circuit.
The above-mentioned input signal A is input into the flip-flop circuit 61 at the timing of a clock signal CLKA, which is extracted from the signal A on the transmission line 57. The Q output of the flip-flop circuit 61 is applied to the variable delay circuit 65 through the fixed delay circuit 64. Then, the signal A is further delayed through the variable delay circuit 65, and the output of the variable delay circuit 65 is input into one input terminal of the exclusive OR circuit 66 in the bit error detecting circuit 55.
The above-mentioned output signal C of the standard circuit 52 is input into the flip-flop circuit 62 at the timing of a clock signal CLKC, which is extracted from the signal C. The delay time in the delay circuit 64 is predetermined based on the aforementioned delay in the circuit 51 and the standard circuit 52, and the delay in the elastic memory 63. The output of the elastic memory 63 is input into the other terminal of the exclusive OR circuit 66.
The Q output of the flip-flop circuit 62 is applied to the variable delay circuit 65 through the elastic memory 63. The Q output of the flip-flop circuit 62 is written in the elastic memory 63 at the timing of the clock signal CLKC, and is read out therefrom at the timing of the clock signal CLKA. Namely, each bit of the signal C is applied to the exclusive OR circuit 66 after being synchronized with the clock signal CLKA.
FIG. 3 shows a construction of the variable delay circuit 65.
In FIG. 3, reference numeral 71 denotes a selector, and 72 denotes a shift register formed by a plurality of flip-flop circuits FF1 to FFn.
The output of the elastic memory 63 is applied to the flip-flop circuit FF1 of the first stage, and the clock signal CLKA is applied to edge triggered input terminals of all the flip-flop circuits FF1 to FFn. The above output of the elastic memory 63, and Q outputs of all the flip-flop circuits FF1 to FFn are respectively applied to n+1 input terminals of the selector 71. These terminals are respectively denoted by "0" to "n". The selector 71 selects one of these inputs as its output in accordance with a select signal from the controller 56. Thus, the delay time in the variable delay circuit 65 can be controlled by the select signal, so that phases of each bit of the signal A through the fixed delay circuit 64 and the variable delay circuit 65, and a corresponding bit of the signal C through the circuit 51, the standard circuit 52, the flip-flop circuit 62, and the elastic memory 63, are synchronized with each other at the exclusive OR circuit 66 in the bit error detecting circuit 55.
In the construction of FIG. 2, the output of the exclusive OR circuit 66 is "0" when both the inputs of the exclusive OR circuit 66 match, is "1" when the inputs are different from each other, and is applied to the data input terminal of the flip-flop circuit 67. The clock signal CLKA is applied to the edge triggered input terminal of the flip-flop circuit 67. Thus, the Q output, which is synchronized with the clock signal CLKA, is "0" when both the inputs of the exclusive OR circuit 66 match, is "1" when the inputs are different from each other and is input into one input terminal of the AND circuit 68. The clock signal CLKA is applied to the other input terminal of the AND circuit 68, and thus, a pulse having a width of a half cycle of the clock signal CLKA, is output as a bit error pulse from the AND circuit 68 every cycle the input bits of the exclusive OR circuit 66 indicate the same values.
FIG. 4 is a flow chart of a control procedure of the controller 56 for phase synchronization pull-in and bit error detection in the prior art.
In the step S1 of FIG. 4, first, the delay in the variable delay circuit 65, which is indicated by the number "m" (m=0-n) of the selected input terminal in the variable delay circuit 65, is set to zero by the select signal.
In the step S2, it is determined whether or not the delay in the variable delay circuit 65 exceeds the maximum delay in the variable delay circuit 65. When it is determined NO, the operation goes to the step S3, and a bit error rate BER1 is measured for a predetermined time .DELTA.t. Then, in the step S4, it is determined whether or not the bit error rate BER1 is larger than a threshold value Th1 (for example, 10.sup.-3). When it is determined YES, the operation goes to the step S5, and the delay in the variable delay circuit 65 is incremented by one cycle of the clock signal CLKA as m.fwdarw.m+1. Then, the operations of steps S2 to S5 are repeated until it is determined that the bit error rate BER1 measured in the step S3 is equal to or smaller than the threshold value Th1.
When it is determined NO in the step S4, i.e., it is determined that the bit error rate BER1 measured in the step S3 is equal to or smaller than the threshold value Th1, it is determined that the phase synchronization pull-in is completed, and the operation goes to the step S6 to start monitoring the operation of the circuit 51. In the step S6, a bit error rate BER2 is measured for a predetermined time .DELTA.T (where .DELTA.T&gt;.DELTA.t). Then, in the step S7, it is determined whether or not the bit error rate BER2 is larger than a threshold value Th2 (for example, 10.sup.-6). When it is determined NO in the step S7, it is determined that the operation of the circuit 51 is normal, and the operation goes to the step S1 for carrying out a phase synchronization pull-in operation and a monitoring operation for another channel or another circuit, and the operations of the steps S1 to S7 are repeated.
When it is determined YES in the step S2, it is determined that the phase synchronization pull-in is impossible for the circuit 51, the operation goes to the step S8, and the operation is switched from the circuit 51 to a stand-by circuit for the circuit 51.
When it is determined YES in the step S7, it is determined that a malfunction has occurred in the circuit 51, the operation goes to the step S8, and the operation is switched from the circuit 51 to a stand-by circuit for the circuit 51.
FIGS. 5A to 5C are timing diagrams of the operation of the circuit in FIGS. 1 to 3.
In FIGS. 5A to 5C, reference A, C, CLKA, and D respectively denote the same signals in the circuit of FIGS. 1 to 3, and Q67 denotes the Q output of the flip-flop circuit 67 of FIG. 2.
FIG. 5A is a timing diagram of an operation when the phase of the input signal A in the exclusive OR circuit 66 precedes the other input signal C by two bits (two cycles of the clock signal CLKA). FIG. 5B is a timing diagram of an operation when the phase of the input signal A in the exclusive OR circuit 66 precedes the other input signal C by one bit (one cycle of the clock signal CLKA). FIG. 5C shows an operation when the phase of the input signal A in the exclusive OR circuit 66 coincides to with the other input signal C.
As shown in FIGS. 5A and 5B, when the phases of the input signals A and C in the exclusive OR circuit 66 differ from each other, usually, the output D of the bit error detecting circuit 55 contains the aforementioned bit error pulse, and thus the bit error rate is increased. On the other hand, as shown in FIG. 5C, when the phases of the input signals A and C in the exclusive OR circuit 66 coincide with each other, the output D of the bit error detecting circuit 55 does not contain the aforementioned bit error pulse, and thus the bit error rate is not increased as long as the circuit being monitored operates normally.
However, in communication systems, a signal consisting of all "1"'s may be transmitted as an alarm indication signal AIS which indicates an occurrence of an alarm state.
FIGS. 6A to 6D are timing diagrams of the conventional control operations of FIG. 4 when an alarm indication signal AIS is successively input from the transmission line 57.
In FIGS. 6A to 6D, reference letters A, C, and D respectively denote the signals which are the same in FIGS. 5A to 5C.
FIG. 6A is a timing diagram when the signal transmitted on the transmission line 57 includes no bit error through the phase synchronization pull-in and monitoring operations. FIGS. 6B to 6D are timing diagrams when the signal transmitted on the transmission line 57 includes no bit error through the phase synchronization pull-in operation, but the signal transmitted on the transmission line 57 includes a bit error during the monitoring operation.
As shown in FIG. 6A, when the signal transmitted on the transmission line 57 includes no bit error through the phase synchronization pull-in and monitoring operations, the bit error rate is zero regardless of the setting of the delay time in the variable delay circuit 65. Namely, the determination in the step S6 is NO regardless of the setting of the delay time in the variable delay circuit 65, and therefore, by the procedure of FIG. 4, it is impossible to know whether or not a correct delay time setting is performed, i.e., the correct delay time is indefinite, as long as the alarm indication signal AIS is used as a signal in the operation.
Further, the phase synchronization pull-in operations are carried out for a shorter time than the period of monitoring, and the threshold value Th1 used in the phase synchronization pull-in operation, is higher than the threshold value Th2 used in the monitoring operation. As shown in FIGS. 6B and 6D, when the delay time setting is incorrectly carried out, the signal transmitted on the transmission line 57 may include no bit error during the short measuring period in the phase synchronization pull-in operation. But, the signal transmitted on the transmission line 57 may include a bit error during the long measuring period in the monitoring operation. Further, generally, the bit error rate BER1 in the phase synchronization pull-in operation may lower than the high threshold value Th1, but the bit error rate BER2 in the phase synchronization pull-in operation may be higher than the low threshold value Th2. In these cases, a normal circuit may be incorrectly determined as a malfunction due to a bit error which is generated on the transmission line, when the delay time setting is incorrectly carried out as shown in FIGS. 6B and 6D.
FIG. 7 is a flow chart of another conventional control procedure of the controller 56 for phase synchronization pull-in and bit error detection, which is provided to solve the above problem regarding the alarm indication signal AIS, and is disclosed in Japanese Unexamined Patent Publication No. 1-175332.
In the step S51 of FIG. 7, the aforementioned phase synchronization pull-in operation in the steps S1 to S5 of FIG. 4, is carried out. In the step S53, it is determined whether or not the phase synchronization pull-in is impossible in the process of FIG. 4. When it is determined impossible, the operation goes to the step S60. The operation of the step S60 in FIG. 7 is the same as the step S8 of FIG. 4.
When it is determined that phase synchronization pull-in is possible in the step S53 of FIG. 7, i.e.,it is determined NO in the step S4 of FIG. 4, the operation goes to the step S54 of FIG. 7, instead of the step S6 of FIG. 4. In the step S54, the delay time setting in the variable delay circuit 65 is shifted by at least one cycle of the clock signal CLKA, for example, as m.fwdarw.m+1. Then a phase synchronization pull-in operation is carried out again for the delay time m+1. Next, in the step S55, it is determined whether or not the above phase synchronization pull-in in the step S54 is successfully carried out by the above shifted delay m+1.
When it is determined NO (impossible) in the step S55, it is determined that the signal on the transmission line is an alarm indication signal AIS, and no following monitoring operation is carried out. Then the operation goes to the step S51 of FIG. 7 (S1 of FIG. 4) for a signal in another channel.
When it is determined YES (possible) in the step S55, it is determined that the signal on the transmission line is not an alarm indication signal AIS, the operation goes to the step S56, and the delay time setting is shifted back to the delay time before the step S54. Then, in the step S57 of FIG. 7 (S6 of FIG. 4), the following monitoring operation is carried out, and the operations of the step 57 and after are the same as the corresponding operations in FIG. 4.
According to the procedure of FIG. 7, an alarm indication signal AIS can be detected before carrying out a monitoring operation using an incorrect delay time which is obtained through the phase synchronization pull-in operation in FIG. 4. The above incorrect determination as a malfunction for a normal circuit can be avoided regarding the alarm indication signal AIS.
However, generally, in communication systems, signals each consisting of a cyclic pattern are used.
FIGS. 8A to 8D, and 9A to 9D are timing diagrams for the circuits in FIGS. 1 to 3, when some signals each consisting of a cyclic pattern are used in the phase synchronization pull-in and monitoring operation.
In the example of FIGS. 8A to 8D, a signal consisting of an alternating pattern "1010 . . . " is used in the bit error detecting operation.
FIG. 8A is a timing diagram when the phase of the input signal A differs from the phase of the input signal C by 2r cycles of the clock signal CLKA at the exclusive OR circuit 66, where r is an arbitrary integer, and no error bit is included in the signal on the transmission line 57.
As shown in FIG. 8A, even when the phase of the input signal A differs from the phase of the input signal C by 2r cycles of the clock signal CLKA at the exclusive OR circuit 66. No bit error pulse appears in the signal D in the case of FIG. 8A, and therefore, the correct delay time cannot be determined, i.e., the correct delay time is indefinite, by the phase synchronization pull-in procedure of the steps S1 to S5 of FIG. 4.
FIG. 8C is a timing diagram where the phases of the input signals A and C coincide with each other at the exclusive OR circuit 66, and an error bit is included in the signal on the transmission line 57.
FIGS. 8B and 8D are timing diagrams where the phase of the input signal A differs from the phase of the input signal C by +4 and -4 cycles of the clock signal CLKA at the exclusive OR circuit 66, respectively, and a error bit is included in the signal on the transmission line 57.
Similar to the cases of FIGS. 6B and 6D, the error bit may not be included in the signal on the transmission line 57 during the phase synchronization pull-in operation, or the bit error rate may be lower than the high threshold value Th1 in the phase synchronization pull-in operation. However, the bit error rate may be higher than the low threshold value Th2 in the monitoring operation. Namely, incorrect delay time setting results in a false determination that a malfunction has occurred in the circuit being monitored, when the bit error rate is between the threshold values Th1 and Th2.
In the example of FIGS. 9A to 9D, a signal consisting of an alternating pattern "11010 . . . ", and having a recurring cycle of five bits, is used in the bit error detecting operation.
FIG. 9A is a timing diagram where the phase of the input signal A differs from the phase of the input signal C by 5r cycles of the clock signal CLKA at the exclusive OR circuit 66, where r is an arbitrary integer. The error bit is included in the signal on the transmission line 57.
As shown in FIG. 9A, even when the phase of the input signal A differs from the phase of the input signal C by 5r cycles of the clock signal CLKA at the exclusive OR circuit 66, no bit error pulse appears in the signal D in the case of FIG. 9A. Therefore, the correct delay time cannot be determined, i.e., the correct delay time is indefinite, by the phase synchronization pull-in procedure of the steps S1 to S5 of FIG. 4
FIG. 9C is a timing diagram where the phases of the input signals A and C coincide with each other at the exclusive OR circuit 66, and an error bit is included in the signal on the transmission line 57.
FIGS. 9B and 9D show the cases where the phase of the input signal A differs from the phase of the input signal C by +4 and -4 cycles of the clock signal CLKA at the exclusive OR circuit 66, respectively, and an error bit is included in the signal on the transmission line 57.
Similar to the cases of FIGS. 6B and 6D, and FIGS. 8B and 8D, the error bit may not be included in the signal on the transmission line 57 during the phase synchronization pull-in operation, or the bit error rate may be lower than the high threshold value Th1 in the phase synchronization pull-in operation. However, the bit error rate may be higher than the low threshold value Th2 in the monitoring operation. Namely, incorrect delay time setting results in a false determination that a malfunction has occurred in the circuit being monitored, when the bit error rate is between the threshold values Th1 and Th2.